Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
4.11
AC Timings for HYB18H256321BF
TABLE 19
Timing Parameters for HYB18H256321BF
Unit Note
Parameter
CAS latency
Symbol Limit Values
–10
–11
–12
–14
Min. Max. Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
System frequency
CL=13
fCK13
fCK12
fCK11
fCK10
fCK9
fCK8
fCK7
tCH
—
—
—
—
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1)
2)
1)
1)
1)
1)
CL= 12
CL= 11
CL =10
CL = 9
CL = 8
CL = 7
TBD 1000
400 900
400 800
400 700
400 600
400 550
—
—
400 900
400 800
400 700
400 600
400 550
400 800
400 700
400 650
400 550
400 500
400
400
400
400
400
700
650
600
500
450
Clock high level width
Clock low-level width
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL
3)
Minimum clock half period
tHP
0.45
—
0.45
—
0.45
—
0.45
—
tCK
Command and Address Setup and Hold Timing
Address/Command input setup time
Address/Command input hold time
Address/Command input pulse width
Mode Register Set Timing
tIS
tIH
tIP
0.24
0.24
0.7
—
—
—
0.27
0.27
0.7
—
—
—
0.3
0.3
0.7
—
—
—
0.35
0.35
0.7
—
—
—
ns
ns
tCK
4)5)
3)
Mode Register Set cycle time
Mode Register Set to READ timing
Row Timing
tMRD
6
—
—
6
—
—
6
—
—
6
—
—
tCK
tCK
tMRDR
12
12
12
12
Row Cycle Time
tRC
37
23
9
—
—
—
—
—
35
22
8
—
—
—
—
—
34
21
8
—
—
—
—
—
30
18
7
—
—
—
—
—
tCK
tCK
tCK
tCK
tCK
tCK
6)
7)
Row Active Time
tRAS
tRRD
tRP
ACT(a) to ACT(b) Command period
Row Precharge Time
14
13
12
13
12
12
11
Row to Column Delay Time for Reads
Row to Column Delay Time for Writes
Column Timing
tRCDRD 13
tRCDWR
tRCDWR(Min) = max(tRCDRD(Min) - (WL + 1) × tCK;2×tCK)
8)
CAS(a) to CAS(b) Command period
Write to Read Command Delay
Read to Write command delay
tCCD
tWTR
tRTW
2
7
—
—
2
6
—
—
2
6
—
—
2
5
—
—
tCK
tCK
tCK
9)
10)
t
RTW(min)= (CL + BL/2 +2 -WL)
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS latching
transition
tDQSS
WL– WL+ WL– WL+ WL– WL+ WL– WL+ tCK
0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25
Rev. 0.80, 2007-09
33
09132007-07EM-7OYI
QIMONDA [ QIMONDA AG ]
