Internet Data Sheet
HYB15T1G[40/80/16]0C2F
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 3
Chip Configuration for x16 Components in FBGA–84, Top View
ꢃ
ꢆ
ꢅ
ꢉ
ꢂ
$
%
&
'
(
)
ꢈ
ꢁ
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9''
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9664
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8'46
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8'46
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9''4
9''4
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9664
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9''4
9''4
9''4
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+
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9''
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Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VSSDL is connected to VSS
internally. VDD, VDDQ and VSSQ are isolated on the device.
Rev. 1.00, 2008-08
16
11202007-1NZ2-6U4E
QIMONDA [ QIMONDA AG ]
