P4C1041L
LOW POWER 256K x 16 (4 MEG)
STATIC CMOS RAM
FEATURES
Fast Access Time - 55 ns
Advanced CMOS Technology
Fast tOE
Low Power Operation
Single 5V±10% Power Supply
2.0V Data Retention
Automatic Power Down when deselected
Packages
Easy Memory Expansion Using CE and OE Inputs
Fully TTL Compatible Inputs and Outputs
– 44-Pin 400 mil TSOP II
DESCRIPTIOꢀ
The P4C1041L is a 262,144 words by 16 bits high-speed
CMOSstaticRAM. TheCMOSmemoryrequiresnoclocks
or refreshing, and has equal access and cycle times. In-
puts are fully TTL-compatible. The RAM operates from a
single 5.0V ± 10% tolerance power supply.
are specified on address pinsA0 toA17. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memorylocationispresentedonthedatainput/outputpins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Access times of 55 nanoseconds permit greatly enhanced
system operating speeds. CMOS is utilized to reduce
power consumption to a low level.
The P4C1041L comes in a 44-Pin 400 mil TSOP II pack-
age.
The P4C1041L device provides asynchronous operation
with matching access and cycle times. Memory locations
FUꢀCTIOꢀAL BLOCꢁ DIAꢂRAM
PIꢀ COꢀFIꢂURATIOꢀ
TSOP II
Document # SRAM142 REV OR
Revised March 2011
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
