PACE 1757 M/ME
PIC REGISTER MAP DEFINITIONS
CONTROL REGISTER (Default = 0000)
I/O READY PROGRAM REGISTER
PR1
PR2
PR3
PR4
Enable Parity Checking/Generation for
Memory Addresses 0000-3FFF.
Enable Parity Checking/Generation for
Memory Addresses 4000-7FFF.
Enable Parity Checking/Generation for
Memory Addresses 8000-BFFF.
Enable Parity Checking/Generation for
Memory Addresses C000-FFFF.
(Default = Undefined)
IO Q1
IO Q2
IO Q3
IO Q4
Lower section number of wait states.
Second section number of wait states.
Third section number of wait states.
Upper section number of wait states.
PROGRAM REGISTER (Default = 0000)
CFB
EBT
SBT
0:5, Clock Frequency Bits (MHz).
Enable Bus Time-out Function.
Select Bus Time-out Limit; 1 = 128
Cycles, 0 = 64 Cycles.
ODD Enable ODD Parity.
EST
Enable Three State Control on PIC
Generated Strobes: IOR, IOW, MEMR,
MEMW.
EWD
SWD
Enable Watch Dog Function.
Select Watch Dog Clock, 1 = 1KHz, 0 =
1MHz.
EAD
EXR
SPI
Enable Three State Control on PIC
Generated Address: A -A .
0
15
Extends ready generation over the full I/O
space when = 1. (Default = 0)
Enables IILEGAL PIO detection for MIL-STD-
1750A spare I/O spaces. 1 = Spare I/O legal,
0 = Default = spare I/O illegal.
EDAC Function on MMU/COMBO; 1 = used,
0 = not used.
Enable Block 1 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register.
Enable Block 2 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register
Enable illegal PIO Detection, as defined in
Last Implemented Input and Output
Registers.
Enable Long I/O Ready Generation, 1ms to
15ms, I/O Addresses 0000-00FF, 8000-
80FF.
Enable Long Memory Ready Generation,
1ms to 15ms, Addresses 0000-3FFF.
WATCH DOG TIMER REGISTER (Default = 0000)
BITS 0:15, Watch Dog set-up Count.
UNIMPLEMENTED MEMORY REGISTER
(Default = Undefined)
CNF
EB1
BL1 LO
BL1 HI
BL2 LO
BL2 HI
Low boundary of unimplemented block
1 of memory.
High boundary of unimplemented block
1 of memory.
Low boundary of unimplemented block
2 of memory.
High boundary of unimplemented block
2 of memory.
EB2
EIO
LIO
FIRST UNIMPLEMENTED OUTPUT COMMAND
REGISTER (Default = Undefined)
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO output
command.
LME
FIRST UNIMPLEMENTED INPUT COMMAND
REGISTER (Default = Undefined)
STATUS REGISTER (Default = 0000)
CPU CPU Passed PIC System Test.
CMB COMBO Chip Passed PIC System Test.
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO input
command.
PIC
STB
PIC Chip Passed PIC System Test.
Reserved.
FIRST FAILING REGISTER (Default = Undefined)
BITS 0:15 16 LSB of the physical address of the
first failure.
ADR Reserved.
TWD Watch Dog reached terminal count.
TBT
IFL
Bus Time-out reached terminal count.
Interrupt Flag-Shows the last interrupt I/O
command implemented in the software.
MEMORY READY PROGRAM REGISTER
(Default = FFFF)
MEM Q1
MEM Q2
MEM Q3
MEM Q4
Lower Block number of wait states.
Second Block number of wait states.
Third Block number of wait states.
Upper Block number of wait states.
Do c um e nt # MICRO-10 REV B
Pa g e 31 o f 34
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
