PACE 1757 M/ME
PIC REGISTER MAP
CONTROL REGISTER (1F40, 9F40)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
PR1 PR2 PR3 PR4 ODD EST EAD EXR
SPI CNF EB1 EB2 EIO
LIO
LME
STATUS REGISTER (9F41)
0
1
2
3
4
5
6
7
8
9
10
10
11
12
13
14
14
14
15
CPU CMB PIC RESERVED STB ADR TWD TBT
RESERVED
IFL
MEMORY READY PROGRAM REGISTER (1F42, 9F42)
0
1
2
3
4
5
6
7
7
7
8
8
8
9
11
11
11
11
11
11
12
12
12
13
15
15
15
15
15
15
15
15
MEM Q1
MEM Q2
MEM Q3
MEM Q4
I/O READY PROGRAM REGISTER (1F43, 9F43)
0
1
2
3
4
5
5
5
6
9
10
IOQ3
13
IO Q1
IO Q2
IO Q4
PROGRAM REGISTER (1F44, 9F44)
0
1
2
3
4
6
9
10
10
10
13
14
14
14
CLOCK FREQUENCY (MHZ)
EBT SBT EWD SWD
RESERVED
WATCH DOG TIMER (1F45, 9F45)
0
1
2
3
4
6
7
8
9
12
12
12
13
13
13
WATCHDOG SETUP COUNT
UNIMPLEMENTED MEMORY REGISTER (1F46, 9F46)
0
1
2
3
4
5
6
7
8
9
BL1 LO
BL1 HI
BL2 LO
BL2 HI
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F47, 9F47)
0
1
2
3
4
5
6
7
8
9
10
14
14
14
X
X
X
X
X
X
FIRST UNIMPLEMENTED OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F48, 9F48)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
X
X
X
X
X
X
FIRST UNIMPLEMENTED INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F49)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
FIRST FAILING ADDRESS
Do c um e nt # MICRO-10 REV B
Pa g e 30 o f 34
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
