PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
FAULTS AND FLAGS
Mnemonic
Name
Description
MEM PRT ER
Memory Protect Error An active-LOW input generated by the MMU or BPU, or both, during
attempted writes to protected memory. It is sampled by the BUS BUSY
signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus
cycle). The error is generated in one of the following conditions: a
mismatchintheaccesskeysintheMMUpage,anaccesstoanexecution
protected page during instruction cycles, an access to a write protected
page during data cycles or an access to a page write protected by the
BPU.
MEM PAR ER
Memory Parity Error
An active LOW signal which is sampled by the BUS BUSY signal into bit
2 of the CPU's Fault Register. It signals an error on the Data Bus during
amemorycycle. Twodetectionmodescanbeselectedbyprogramming
thecontrolregisteroftheMMU/COMBO:EDACmode(6Hammingcode
parity bits) or single bit parity mode (even or odd parity). The signal is
inactivewhennoneoftheabovemodesareselected(defaultafterreset).
EXT ADR ER IN External Address
An active-LOW input sampled by the BUS BUSY signal into the CPU
Error In
Fault Register (bit 5 or 8) depending on the cycle (memory or I/O).
EXT ADR ER OUT External Address
An active LOW output which signals to the CPU and memory interface
logic that an unimplemented memory or illegal I/O access has taken
place.
Error Out
SYSFLT -
System Fault 0,
System Fault 1
Asynchronous, positive edge sensitive inputs that set bit 7 (SYSFLT )
0
0
SYSFLT
or bits 13 and 15 (SYSFLT ) in the P1750A/AE Fault Register.
1
1
EX AD ER /
Illegal Address Error / An active LOW output from the PIC indicating an illegal address error
SING ERR
Single Error
whenreferencingmemoryorI/O. ItbecomesanactiveHIGHinputcalled
SINGLE ERROR for handshaking with the P1753 when the PIC is
programmedtosupportEDAC. Defaultstateafterresetishighimpedance.
WR PROT /
Write Protected /
Protection Flag
Either an active LOW output (WR PROT, following STRBD timing)
duringlegalmemorywritecycleswhennoprotectionoccurs,oranactive
high (PROT FLAG) signal indicating a protection error in a write cycle.
Either mode can be selected by programming the COMBO control
register. Default mode after reset is Write Protected.
PROT FLAG
ME PA ER /
Memory Parity Error
Terminal Count
An active LOW output indicating a Parity error when reading from
memory. It becomes an active HIGH output called RAM DISABLE for
handshaking with the P1753 when the PIC is programmed to support
EDAC.
RAMDIS
TC
An active HIGH output from the PIC indicating a bus time out or a
watchdog trigger.
Do c um e nt # MICRO-10 REV B
Pa g e 25 o f 34
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