PACE 1757 M/ME
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
Asinglephaseinputclocksignal(0-40MHz,40percentto60percentduty
cycle. This is a common input to all 3 devices.
RESET
Reset
An active LOW input that initializes the device. Input to the P1750A/AE,
P1753 and P1754.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction. Input to the CPU.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register of the P1750A/AE.
USR INT -
User interrupt
Interrupt request input signals that are active on the positive going edge
edgeorthehighlevel,accordingtotheinterruptmodebitintheconfiguration
register of the P1750A/AE.
0
USR INT
5
IOL INT -
I/O Level Interrupts
Active HIGH interrupt requests that can be used to expand the number
of user interrupts. Inputs to the P1750A/AE interrupt register.
1
IOL INT
2
ERROR CONTROL
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable. A signal from the CPU.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major. A signal from the CPU.
DISCRETE CONTROL
Mnemonic
Name
Description
NML PWRUP
Normal power up
An active HIGH output that is set when the CPU has successfully
completedthebuilt-inselftestintheinitializationsequence. Itcanbereset
by the I/O command RNS.
SNEW
Start new
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle. This signal is issued by the CPU.
TRIGO RST
Trigger-go reset
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
STRT ROM
Start Up Rom
An output follow the execution of the ESUR and DSUR, I/O commands as
defined in MIL-STD-1750A. It will be at the logical level "1" after executing
ESURandatthelogical"0"levelafterexecutingDSUR. Initially,itdefaults
to a "1" on the P1754.
DMA EN
Direct memory
Access enable
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
Do c um e nt # MICRO-10 REV B
Pa g e 22 o f 34
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
