PACE1750A
TERMINAL CONNECTIONS
Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with Gull-
Wing Leads (Case Y)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
1
2
GND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
IB
IB
IB
IB
IB
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
AS
AS
AS
11
12
13
14
15
2
1
0
CON REQ
DMA EN
TRIGO RST
RESET
3
4
GND
5
AK
AK
3
2
6
NML PWRUP
TIMER CLK
UNRCV ER
GND
MEM PRT ER
MEM PAR ER
EXT ADR ER
7
VCC
8
AK
AK
1
0
9
SYSFLT
SYSFLT
MAJ ER
GND
0
1
10
11
12
13
14
15
16
17
18
19
20
21
22
IB
IB
IB
IB
IB
IB
IB
IB
CPU CLK
STRBA
STRBD
BUS REQ
RDYA
0
1
2
3
4
5
6
7
VCC
PWRDN INT
USR INT
RDYD
0
USR INT
R/W
1
USR INT
D/I
2
GND
USR INT
M/IO
3
IB
IB
USR INT
BUS BUSY
BUS GNT
BUS LOCK
8
9
4
USR INT
5
VCC
IB
IOL INT
1
44
45
IOL INT
67
68
SNEW
VCC
10
2
AS
3
Do c um e nt # MICRO-3 Re v. C
Pa g e 16 o f 24
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
