PACE1750A
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
D/I
Data or instruction
Anoutputsignalthatindicateswhetherthecurrentbuscycleaccessisfor
Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not
assigned to the CPU. This line can be used as an additional memory
address bit for systems that require separate data and program memory.
R/W
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOWindicatesawriteoroutputoperation. Thesignalisthree-stateduring
bus cycles not assigned to the CPU.
M/IO
Memory or I/O
Address strobe
Address ready
Data strobe
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to the CPU.
STRBA
RDYA
STRBD
RDYD
An active HIGH output that can be used to externally latch the memory or
I/O address at the HIGH-to-LOW transition of the strobe. The signal is
three-state during bus cycles not assigned to the CPU.
An active HIGH input that can be used to extend the address phase of a
buscycle. WhenRDYAisnotactive,waitstatesareinsertedbythedevice
to accommodate slower memory or I/O devices.
AnactiveLOWoutputthatcanbeusedtostrobedatainmemoryandXIO
cycles. This signal is three-state during bus cycles not assigned to the
CPU.
Data ready
An active HIGH input that extends the data phase of a bus cycle. When
RDYDisnotactive,waitstatesareinsertedbythedevicetoaccommodate
slower memory or I/O devlces.
INFORMATION BUS
Mnemonic Name
IB - IB
Description
Information bus
A bidirectional time-multiplexed address/data bus that is three-state
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15
during bus cycles not assigned to the CPU. IB is the most significant bit.
0
STATUS BUS
Mnemonic
Name
Description
AK - AK
Access key
Outputs used to match the access lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicates processor state (PS). Privileged instructions can be
executed with PS = 0 only. These signals are three-state during bus
cycles not assigned to the CPU.
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3
AS - AS
Address state
Outputs that select the page register group in the MMU. It is three-state
during bus cycles not assigned to the CPU. [These outputs together with
D/I can be used to expand the device direct addressing space to 4
MBytes, in a nonprotected mode (no MMU)]. However, using this
addressingmodemayproducesituationsnotspecifiedinMIL-STD-1750.
0
3
Do c um e nt # MICRO-3 Re v. C
Pa g e 13 o f 24
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
