May 2007
rev 0.2
PCS5P23Z05B/09B
Input-Output Skew
Test Circuit
Timing-Safe™
Output
Input
TEST CIRCUIT
+3.3V
+3.3V
VDD
LOAD
TSKEW
+
TSKEW
-
0.1uF
0.1uF
OUTPUTS
VDD
One clock cycle
N=1
GND
GND
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock 32MHz, translates in to
(1/32MHz) * 0.125=3.90nS
A Typical example of Timing-Safe™ waveform
Input
Input
CLKOUT with SSOFF
Timing-Safe™ CLKOUT
Timing-Safe™ Peak EMI Reduction IC
7 of 14
Notice: The information in this document is subject to change without notice.