May 2007
rev 0.2
PCS5P23Z05B/09B
Switching Characteristics for PCS5P23Z05B and PCS5P23Z09B
Parameter
Description
Output Frequency
Test Conditions
Min
20
Typ
Max Unit
1/t1
30pF load
50
MHz
Duty Cycle 2 = (t2 / t1) * 100
Output Rise Time1, 2
Measured at VDD/2
40
50
60
%
t3
t4
t5
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
2.5
2.5
250
nS
nS
pS
Output Fall Time1, 2
Output-to-output skew 2
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge 2
t6
Measured at VDD /2
±350
pS
Measured at VDD/2 on the CLKOUT pins
of the device
t7
tJ
Device-to-Device Skew 2
700
200
1.0
pS
pS
Cycle-to-cycle jitter 2
PLL Lock Time 2
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
tLOCK
mS
Note: 1. The parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Timing-Safe™ Peak EMI Reduction IC
5 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
