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PCS3P622S04JG-08-TR 参数 Datasheet PDF下载

PCS3P622S04JG-08-TR图片预览
型号: PCS3P622S04JG-08-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 低频定时- SAFE™峰值EMI降低IC [Low Frequency Timing-Safe™ Peak EMI reduction IC]
分类和应用: 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
文件页数/大小: 10 页 / 540 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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May 2007  
rev 0.3  
PCS3P622S04J  
Electrical Characteristics  
Parameter  
Description  
Test Conditions  
Min  
Typ  
Max  
0.8  
Unit  
V
VIL  
VIH  
IIL  
Input LOW Voltage1  
Input HIGH Voltage1  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage2  
Output HIGH Voltage2  
Supply Current  
2.0  
V
VIN = 0V  
50  
100  
0.4  
µA  
µA  
V
IIH  
VIN = VDD  
VOL  
VOH  
IDD  
Zo  
IOL = 8mA  
IOH = -8mA  
Unloaded outputs  
2.4  
V
14  
23  
mA  
Output Impedance  
Note: 1. REF input has a threshold voltage of V /2  
DD  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production  
Switching Characteristics  
Parameter  
Description  
Test Conditions  
Min  
Typ  
Max Unit  
1/t1  
Output Frequency  
30pF load  
4
20  
MHz  
Duty Cycle 2 = (t2 / t1) * 100  
Output Rise Time 1,2  
Measured at VDD/2  
40  
50  
60  
%
t3  
t4  
t5  
Measured between 0.8V and 2.0V  
Measured between 2.0V and 0.8V  
All outputs equally loaded  
2.5  
2.5  
250  
nS  
nS  
pS  
Output Fall Time 1,2  
Output-to-output skew 2  
Delay, REF Rising Edge to  
CLKOUT Rising Edge 2  
t6  
Measured at VDD /2  
±350  
pS  
Measured at VDD/2 on the CLKOUT pins  
of the device  
t7  
tJ  
Device-to-Device Skew 2  
Cycle-to-cycle jitter 2  
PLL Lock Time 2  
700  
200  
1.0  
pS  
pS  
Loaded outputs  
Stable power supply, valid clock presented  
on REF pin  
tLOCK  
mS  
Note: 1. All parameters specified with loaded outputs.  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production  
Low Frequency Timing-Safe™ Peak EMI Reduction IC  
4 of 10  
Notice: The information in this document is subject to change without notice.