May 2007
rev 0.3
PCS3P622S04J
Low Frequency Timing-Safe™ Peak EMI reduction IC
General Features
with Peak EMI Reduction. PCS3P622S04J accepts one
reference input and drives out four low-skew clocks.
PCS3P622S04J has an on-chip PLL that locks to an input
clock on the XIN/CLKIN pin. The PLL feedback is on-chip
and is obtained from the CLKOUT pad, internal to the
device. PCS3P622S04J has a crystal oscillator interface.
An inexpensive crystal will provide the clock source for
distribution. It is available in 8 pin TSSOP.
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Low Frequency Clock Distribution with Timing-
Safe™ and Peak EMI Reduction
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Input frequency range: 4MHz - 20MHz
Zero input - output propagation delay
Low-skew outputs
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Output-output skew less than 250pS
Device-device skew less than 700pS
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Less than 200pS Cycle-to-cycle jitter
3.3V Operation
Commercial temperature range
Available in 8pin TSSOP(4.4MM-Body)
First True Drop-in solution
All outputs have less than 200pS of Cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 350pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Refer “Spread Spectrum Control and Input-Output Skew
Table” for values of deviation and Input-Output Skew
Product Description
PCS3P622S04J is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
Block Diagram
VDD
CLK1
CLKIN / XIN
XOUT
CLK2
Crystal
PLL
Oscillator
CLK3
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
