September 2006
rev 0.2
PCS2P5T915A
VDDQ
R1
VDDQ
VDD
VDDQ
VDDQ
R2
CL
R1
R2
D.U.T.
Qn
Qn
D.U.T.
CL
VDDQ
Qn
R1
R2
CL
Test Circuit for SDR Outputs
Test Circuit for Differential Outputs
Differential Output Test Contions
SDR Output Test Conditions
VDD= 2.5V ± 0.1V
Symbol
VDDQ= Interface
Unit
VDD= 2.5V ± 0.1V
Symbol
Unit
Specified
15
VDDQ= Interface Specified
C L
R1
pF
Ω
Ω
V
C L
R1
R2
15
pF
Ω
100
100
100
R2
100
Ω
VTHO
VDDQ/ 2
HSTL: Crossing of Qn and Qn
VOX
V
V
eHSTL: Crossing of Qn and Qn
1.8V LVTTL: VDDQ/2
VTHO
2.5V LVTTL: VDDQ/2
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
20 of 23
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
