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ASM2P5T905AG-28TR 参数 Datasheet PDF下载

ASM2P5T905AG-28TR图片预览
型号: ASM2P5T905AG-28TR
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V单倍数据速率1 : 5时钟缓冲器TERABUFFER [2.5V Single Data Rate 1:5 Clock Buffer Terabuffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 19 页 / 682 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006
rev 0.2
DC Electrical Characteristics over Operating Range
Symbol
V
IHH
V
IMM
V
ILL
I
3
ASM2P5T905A
Parameter
Input HIGH Voltage Level
Input MID Voltage Level
1
Input LOW Voltage Level
1
3-Level Input DC Current
(RxS, TxS)
1
Test Conditions
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
HIGH Level
V
IN
= V
DD
/2
MID Level
V
IN
= GND
LOW Level
Min
V
DD-
0.4
V
DD
/2- 0.2
Max
V
DD
/2 + 0.2
0.4
200
+50
Unit
V
V
V
µA
-50
-200
NOTE:
1. These inputs are normally wired to V
DD
, GND, or left floating. Internal termination resistors bias unconnected inputs to V
DD
/2.
DC Electrical Characteristics over Operating Range for HSTL
1
Symbol
Parameter
Input Characteristics
I
IH
I
IL
V
IK
V
IN
V
DIF
V
CM
V
IH
V
IL
V
REF
Input HIGH Current
9
Input LOW Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage
2,8
DC Common Mode Input
Voltage
3,8
4,5,8
DC Input HIGH
DC Input LOW
4,6,8
Single-Ended Reference
Voltage
4,8
Output HIGH Voltage
Output LOW Voltage
9
Test Conditions
V
DD
= 2.6V
V
I
= V
DDQ
/GND
Min
Typ
7
Max
±5
Unit
µA
V
V
V
mV
mV
mV
mV
V
V
DD
= 2.6V
V
I
= GND/V
DDQ
V
DD
= 2.4V, I
IN
= -18mA
-0.3
0.2
680
V
REF
+ 100
-0.7
±5
- 1.2
+3.6
900
V
REF
-100
750
750
I
OH
= -8mA
I
OH
= -100µA
I
OL
= 8mA
I
OL
= 100µA
V
DDQ
- 0.4
V
DDQ
- 0.1
0.4
0.1
Output Characteristics
V
OH
V
OL
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
3. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/V
REF
is tied to the DC voltage V
REF
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
9. For differential mode (RxS = LOW), A and A/V
REF
must be at the opposite rail
.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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