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ASM2P5T905AG-28TR 参数 Datasheet PDF下载

ASM2P5T905AG-28TR图片预览
型号: ASM2P5T905AG-28TR
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V单倍数据速率1 : 5时钟缓冲器TERABUFFER [2.5V Single Data Rate 1:5 Clock Buffer Terabuffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 19 页 / 682 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006
rev 0.2
Differential Input AC Test Conditions for eHSTL
Symbol
V
DIF
V
X
V
THI
t
R
, t
F
Input Signal Swing
1
ASM2P5T905A
Parameter
Differential Input Signal Crossing Point
2
Input Timing Measurement Reference Level
3
Input Signal Edge Rate
4
Value
1
900
Crossing Point
1
Units
V
mV
V
V/nS
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in automatic test equipment (ATE) environment. Compliant devices
must meet the V
DIF
(AC) specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the V
X
specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics over Operating Range for LVEPECL
1
Symbol
Parameter
Input Characteristics
I
IH
I
IL
V
IK
V
IN
V
CM
V
REF
V
IH
V
IL
Test Conditions
V
DD
= 2.6V
V
I
= V
DDQ
/GND
V
DD
= 2.6V
V
I
= GND/V
DDQ
V
DD
= 2.4V, I
IN
= -18mA
Min
Typ
2
Max
±5
±5
- 1.2
3.6
1248
Unit
µA
V
V
mV
mV
Input HIGH Current
6
Input LOW Current
6
Clamp Diode Voltage
DC Input Voltage
DC Common Mode Input
Voltage
3,5
Single-Ended Reference
4,5
Voltage
DC Input HIGH
DC Input LOW
- 0.7
- 0.3
915
1082
1082
1275
555
1620
875
mV
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at V
DD
= 2.5V, +25°C ambient.
3. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation while in differential mode, A/V
REF
is tied to the DC voltage V
REF
.
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
6. For differential mode (RxS = LOW), A and A/V
REF
must be at the opposite rail.
Differential Input AC Test Conditions for LVEPECL
Symbol
V
DIF
V
X
V
THI
t
R
, t
F
Input Signal Swing
1
2
3
Parameter
Differential Input Signal Crossing Point
Input Signal Edge Rate
4
Value
732
1082
Crossing Point
1
Units
mV
mV
V
V/nS
Input Timing Measurement Reference Level
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the V
DIF
(AC) specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the V
X
specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform
.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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