November 2006
rev 0.2
Pin Description
Symbol
A
ASM2P5T905A
I/O
I
Type
Adjustable
1
Description
Clock input. A is the "true" side of the differential clock input. If operating in single-ended
mode, A is the clock input.
Complementary clock input. A / V
REF
is the "complementary" side of A if the input is in
differential mode. If operating in single-ended mode, A/V
REF
is connected to GND. For
single-ended operation in differential mode, A/V
REF
should be set to the desired toggle
voltage for A:
2.5V LVTTL
V
REF
= 1250mV
1.8V LVTTL, eHSTL V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
Gate control for Qn outputs. When
G
is LOW, these outputs are enabled. When
G
is
HIGH, these outputs are asynchronously disabled to the level designated by GL
4
.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs
disable LOW.
Clock outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential
(LOW) clock input
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID)
or HSTL (LOW) compatible. Used in conjunction with V
DDQ
to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, V
DDQ
should be
connected to V
DD
.
Power supply return for all power
A / V
REF
I
Adjustable
1
G
GL
Qn
RxS
TxS
V
DD
V
DDQ
GND
I
I
O
I
I
LVTTL
5
LVTTL
5
Adjustable
2
3 Level
3
3 Level
3
PWR
PWR
PWR
NOTES: 1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQ
voltage.
3. 3 level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize
the possibility of runt pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
Absolute Maximum Ratings
1
Symbol
V
DD
V
DDQ
V
I
V
O
V
REF
T
STG
T
J
Power Supply Voltage
Output Power Supply
2
Input Voltage
Output Voltage
3
Reference Voltage
3
Storage Temperature
Junction Temperature
2
Description
Max
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
-0.5 to V
DDQ
+0.5
-0.5 to +3.6
-65 to +165
150
Unit
V
V
V
V
V
°C
°C
Note:
1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device
reliability.
2. V
DDQ
and V
DD
internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
