PE43704
Product Specification
Typical Performance Data, 0.5 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 11. 0.5 dB Step Attenuation vs. Frequency*
0.5
0.2GHz
0.25
0.9GHz
1.8GHz
2.2GHz
0
3GHz
4GHz
5GHz
6GHz
7GHz
‐0.25
‐0.5
0
4
8
12
16
20
24
28
32
Attenuation Setting (dB)
* Monotonicity is held so long as step-attenuation does not cross below –0.5 dB
Figure 12. 0.5 dB Step, Actual vs. Frequency
35
30
0.9GHz
25
20
15
10
5
1.8GHz
2.2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
0
0
4
8
12
16
20
24
28
32
Ideal Attenuation (dB)
Figure 14. 0.5 dB Attenuation Error vs.
Frequency
Figure 13. 0.5 dB Major State Bit Error vs.
Attenuation Setting
1.5
1.5
0.2GHz
0.9GHz
1.8GHz
2.2GHz
3GHz
0.5dB
1dB
1
1
2dB
0.5
0
0.5
0
4dB
4GHz
8dB
5GHz
16dB
31.5dB
6GHz
7GHz
‐0.5
‐0.5
0
1
2
3
4
5
6
7
0
4
8
12
16
20
24
28
32
Frequency (GHz)
Attenuation Setting (dB)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-16514-6 |
UltraCMOS® RFIC Solutions
Page 12 of 20
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