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PE43704DS 参数 Datasheet PDF下载

PE43704DS图片预览
型号: PE43704DS
PDF下载: 下载PDF文件 查看货源
内容描述: UltraCMOS® RF数字步进衰减器, 7位, 31.75分贝与可选VssEXT旁路模式为9 kHz - 8 GHz的 [UltraCMOS® RF Digital Step Attenuator, 7-bit, 31.75 dB with Optional VssEXT Bypass Mode 9 kHz - 8 GHz]
分类和应用: 衰减器
文件页数/大小: 20 页 / 731 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE43704
Product Specification
Table 6. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Digital input voltage
RF input power, max
Storage temperature range
ESD voltage HBM
1
, all pins
ESD voltage MM
2
, all pins
ESD voltage CDM
3
, all pins
Notes:
Switching Frequency
Max
5.5
3.6
+34
Unit
V
V
dBm
°C
V
V
V
Symbol
V
DD
V
CTRL
P
MAX,ABS
T
ST
V
ESD,HBM
V
ESD,MM
V
ESD,CDM
Min
-0.3
-0.3
-65
+150
1500
200
250
The PE43704 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 20 = GND). The rate at which the
PE43704 can be switched is only limited to the
switching time (Tables
1-3)
if an external negative
supply is provided (pin 20 = Vss
EXT
).
Switching frequency is defined to be the speed at
which the DSA can be toggled across attenuation
states. Switching time is the time duration
between the point the control signal reaches 50%
of the final value and the point the output signal
reaches within 10% or 90% of its target value.
Optional External Vss Control (Vss
EXT
)
For proper operation, the Vss
EXT
control pin must
be grounded or tied to the Vss voltage specified in
Table 5.
When the Vss
EXT
control pin is grounded,
FETs in the switch are biased with an internal
voltage generator. For applications that require
the lowest possible spur performance, Vss
EXT
can
be applied externally to bypass the internal
negative voltage generator.
Table 7. Latch and Clock Specifications
Latch Enable
0
Shift Clock
X
Function
Shift register clocked
Contents of shift register
transferred to attenuator core
1. Human Body Model (MIL-STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE43704 in the 5x5 QFN package is MSL1.
Safe Attenuation State Transitions
The PE43704 features a novel architecture to
provide safe transition behavior when changing
attenuation states. When RF input power is
applied, positive output power spikes are
prevented during attenuation state changes by
optimized internal timing control.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 20
Document No. DOC-16514-6 |
UltraCMOS
®
RFIC Solutions