PE43704
Product Specification
Figure 5. Serial Timing Diagram
Bits can either be set to logic high or logic low
D[7] must be set to logic low
DI[6:0]
T
DISU
T
DIH
P/S
T
PSSU
T
PSIH
SI
T
SISU
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
T
SIH
CLK
T
CLKL
T
CLKH
T
LESU
LE
T
LEPW
T
PD
DO[6:0]
VALID
Figure 6. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
T
PSSU
T
PSH
VALID
T
DISU
T
DIH
DI[6:0]
LE
T
LEPW
DO[6:0]
T
DIPD
VALID
T
PD
Table 12. Serial Interface AC Characteristics
V
DD
= 3.4V or 5.0V, -40°C < T
A
< 85°C, unless otherwise specified
Parameter
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
Last serial clock rising edge setup
time to Latch Enable rising edge
Latch enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Address hold time
Parallel/serial setup time
Parallel/serial hold time
Digital register delay (internal)
Symbol
F
CLK
T
CLKH
T
CLKL
T
LESU
T
LEPW
T
SISU
T
SIH
T
DISU
T
DIH
T
ASU
T
AH
T
PSSU
T
PSH
T
PD
Min
-
30
30
10
30
10
10
100
100
100
100
100
100
-
Max
10
-
-
-
-
-
-
-
-
-
-
-
-
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 13. Parallel and Direct Interface
AC Characteristics
V
DD
= 3.4V or 5.0V, -40°C < T
A
< 85°C, unless otherwise
specified
Symbol
T
LEPW
T
DISU
T
DIH
T
PSSU
T
PSIH
T
PD
T
DIPD
Parameter
Latch enable minimum pulse
width
Parallel data setup time
Parallel data hold time
Parallel/serial setup time
Parallel/serial hold time
Digital register delay (internal)
Digital register delay (internal,
direct mode only)
Min
30
100
100
100
100
-
-
Max
-
-
-
-
-
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
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UltraCMOS
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RFIC Solutions
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