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PE43704DS 参数 Datasheet PDF下载

PE43704DS图片预览
型号: PE43704DS
PDF下载: 下载PDF文件 查看货源
内容描述: UltraCMOS® RF数字步进衰减器, 7位, 31.75分贝与可选VssEXT旁路模式为9 kHz - 8 GHz的 [UltraCMOS® RF Digital Step Attenuator, 7-bit, 31.75 dB with Optional VssEXT Bypass Mode 9 kHz - 8 GHz]
分类和应用: 衰减器
文件页数/大小: 20 页 / 731 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE43704
Product Specification
Figure 3. Pin Configuration (Top View)
Table 5. Operating Ranges
Parameter
Supply voltage (normal
mode, Vss
EXT
= 0V)
1
Supply voltage (bypass
mode, Vss
EXT
= -3.4V,
V
DD
3.4V for full spec.
compliance)
2
Negative supply voltage
(bypass mode)
2
Supply current (normal
mode, Vss
EXT
= 0V)
1
Supply current (bypass
mode, Vss
EXT
= -3.4V)
2
Negative supply current
(bypass mode, Vss
EXT
=
-3.4V)
2
Symbol
V
DD
Min
2.3
Typ
Max
5.5
Unit
V
V
DD
2.7
3.4
5.5
V
Vss
EXT
I
DD
I
DD
I
SS
V
IH
V
IL
I
CTRL
P
MAX,CW
-3.6
130
50
-40
1.17
-0.3
-16
-2.4
200
80
V
μA
μA
μA
3.6
0.6
15
see
Fig. 4
+28
see
Fig. 4
+31
V
V
μA
dBm
dBm
dBm
dBm
°C
Table 4. Pin Descriptions
Pin #
1
2
3
4
5, 6,
8-17, 19
7
18
20
21
22
23
24
25
26
27
28
29
30
31
32
Pad
Pin Name
N/C
V
DD
P/S
A0
GND
RF1
1
Digital input high
Description
Digital input low
Digital input current
RF input power, CW
3
9 kHz < 50 MHz
50 MHz
8 GHz
No connect
Supply voltage
Serial/parallel mode select
Address bit A0 connection
Ground
RF1 port (RF input)
RF2 port (RF output)
External Vss negative voltage control
Address bit A2 connection
Address bit A1 connection
Serial interface latch enable input
Serial interface clock input
Serial interface data input
Parallel control bit, 16 dB
Parallel control bit, 8 dB
Parallel control bit, 4 dB
Parallel control bit, 2 dB
Parallel control bit, 1 dB
Parallel control bit, 0.5 dB
RF input power, pulsed
4
9 kHz < 50 MHz P
MAX,PULSED
50 MHz
8 GHz
Operating temperature
range
Notes:
T
OP
-40
25
+85
RF2
1
Vss
EXT2
A2
A1
LE
CLK
SI
C16 (D6)
3
C8 (D5)
3
C4 (D4)
3
C2 (D3)
3
C1 (D2)
3
C0.5 (D1)
3
1. Normal mode: connect Vss
EXT
(pin 20) to GND (Vss
EXT
= 0V) to
enable internal negative voltage generator
2. Bypass mode: use Vss
EXT
(pin 20) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50Ω
4. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
C0.25 (D0)
3
Parallel control bit, 0.25 dB
GND
Exposed pad: ground for proper operation
Notes: 1. RF pins 7 and 18 must be at 0V DC. The RF pins do not require DC
blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use Vss
EXT
(pin 20) to bypass and disable internal
negative voltage generator. Connect Vss
EXT
(pin 20) to GND (Vss
EXT
= 0V)
to enable internal negative voltage generator
3. Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use
Document No. DOC-16514-6 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
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