InnoSwitch-CH
4. Reducing the AC flux density (∆B) of the transformer will also lead
to reduction in audible noise from the core.
5. If the secondary-winding is terminated with flying leads verify if
the wires as vibrating against the bobbin or each other.
Iꢂ
Iꢁ
ꢀꢁ ≡ ꢀꢂꢁ
ꢀ
6. If the circuit board shows any signs of pulse bunching (multiple
switching cycles followed by no switching activity), this could be
a cause of audible noise. Pulse bunching can be caused by
incorrect circuit board layout in which the feedback node is being
affected by switching noise. Guidelines provided for FEEDBACK
pin decoupling and the phase lead RC network described in this
note can be evaluated. Verify the board layout recommendations
associated with feedback divider network have been followed.
ꢁR
ꢁꢂ
ꢁꢌiꢓꢄꢌꢔ
ꢃꢄꢅ Continꢆoꢆꢇꢈ ꢀꢁ < ꢉ
Recommendations for Transformer Design
ꢁꢂ
ꢁR
ꢁꢌiꢓꢄꢌꢔ
Transformer design must ensure that the power supply is able to
deliver the rated power at the lowest operating voltage. The lowest
voltage on the rectified DC bus of the power supply depends on the
capacitance of the filter capacitor used. At least 2 mF / W is recom-
mended to keep the DC bus voltage always above 70 V though 3 mF/W
provides sufficient margin. The ripple on the DC bus should be
measured and care should be taken to verify this voltage to confirm
the design calculations for transformer primary-winding inductance
selection.
ꢃꢊꢅ ꢋoꢌꢍꢎꢌꢏinꢎ Continꢆoꢆꢇꢐꢑiꢇcontinꢆoꢆꢇꢈ ꢀꢁ ꢒ ꢉ
ꢂꢁꢃꢄꢅꢆ7ꢃ10ꢇ11ꢈ
Figure 21. Continuous Mode Current Waveform, KP ≤1.
Reflected Output Voltage, VOR (V)
charger designs are often thermally challenged due to the small
enclosure requirement.
This parameter is the secondary-winding voltage during the diode/SR
conduction time reflected back to the primary through the turns ratio
of the transformer. A VOR of 60 V is ideal for most 5 V only designs.
For design optimization purposes, the following should be kept in mind:
Safety Margin, M (mm)
For designs that require safety isolation between primary and
secondary but are not using triple insulated wire the width of the
safety margin to be used on each side of the bobbin should be
entered here. Typically for universal input designs a total margin of
6.2 mm would be required, and a value of 3.1 mm would be entered
into the spreadsheet. For vertical bobbins the margin may not be
symmetrical, however if a total margin of 6.2 mm were required then
3.1 mm would still be entered even if the physical margin were only
on one side of the bobbin.
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch-CH device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR MOSFTs.
3. Higher VOR increases leakage inductance that reduces efficiency
of the power supply.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
For designs using triple insulated wire it may still be necessary to use
a small margin in order to meet the required safety creepage
distances. Typically many bobbins exist for each core size and each
will have different mechanical spacing. Refer to the bobbin data
sheet or seek guidance from your safety expert or transformer
vendor to determine what specific margin is required.
Ripple to Peak Current Ratio, KP
Below a value of 1, indicating continuous conduction mode, KP is the
ratio of ripple to peak primary current (Figure 21)
IR
IP
KP / KRP
=
As the margin reduces the available area for the windings, margin
construction may not be suitable for small core sizes. It is recom-
mended that for compact charger designs using an InnoSwitch-CH
IC, triple insulated wire should be used for secondary which then
eliminates need for margins.
Following a value of 1, indicating discontinuous conduction mode, KP
is the ratio of primary MOSFET off time to the secondary diode
conduction time.
^
h
1 - D # T
KP / KDP
=
Primary Layers, L
t
Primary layers should be in the range of 1 < L < 3 and in general it
should be the lowest number that meets the primary current density
limit (CMA). Values of ≥200 Cmils/Amp can be used as a starting
value for most designs though higher values may be required based
on thermal design constraints. Values above 3 layers are possible but
the increased leakage inductance and physical fit of the windings
should be considered. A split primary construction may be helpful for
designs where leakage inductance clamp dissipation is too high.
In split primary construction, half of the primary winding is placed on
either side of the secondary (and bias) winding in a sandwich
arrangement. This arrangement is often disadvantageous for low
power charger designs as this typically requires additional common
mode filtering which increases cost.
^
h
V
OR # 1 - DMAX
=
VMIN - VDS # DMAX
It is recommended that a KP close to 0.9 at the minimum DC bus
voltage of 70 V should be used for most InnoSwitch-CH designs.
A KP value of <1 results in higher transformer efficiency by lowering
the primary RMS current but results in higher switching losses in the
primary-side MOSFET resulting in higher InnoSwitch-CH temperature.
Core Type
Choice of suitable core is dependent on the physical design
constraints of the enclosure to be used for the charger. It is
recommended that cores with low loss should only be used as
14
Rev. J 10/17
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