TISPPBL2SD
PROGRAMMABLE OVERVOLTAGE PROTECTORS
FOR ERICSSON COMPONENTS PBL 3xxx SLICS
AUGUST 1999
available from the overvoltage, then the thyristor will crowbar into a low voltage ground referenced on-state
condition. As the overvoltage subsides the high holding current of the crowbar thyristor prevents d.c. latchup.
The negative protection voltage will be the sum of the gate supply (V
BAT
) and the peak gate(terminal)-cathode
voltage (V
GK(BO)
). Under a.c. overvoltage conditions V
GK(BO)
will be less than 3 V. The integrated transistor
buffer in the TISPPBL2S greatly reduces protectors source and sink current loading on the V
BAT
supply.
Without the transistor, the thyristor gate current would charge the V
BAT
supply. An electronic power supply is
not usually designed to be charged like a battery. As a result, the electronic supply would switch off and the
thyristor gate current would provide the SLIC supply current. Normally the SLIC current would be less than
the gate current, which would cause the supply voltage to increase and destroy the SLIC by a supply
overvoltage. The integrated transistor buffer removes this problem.
Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection
voltage under impulse conditions will also be increased if there is a long connection between the gate
decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (I
G
) is
the same as the cathode current (I
K
). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of
printed wiring track. To minimise this inductive voltage increase of protection voltage, the length of the
capacitor to gate terminal tracking should be minimised. Inductive voltages in the protector cathode wiring
can increase the protection voltage. These voltages can be minimised by routing the SLIC connection via the
protector as shown in Figure 13 and Figure 14.
Positive overvoltages (Figure 14) are clipped to ground by forward conduction of the diode section in the
TISPPBL2S. Fast rising impulses will cause short term overshoots in forward voltage (V
FRM
).
TISPPBL2S limiting voltages
This clause details the TISPPBL2S voltage limiting levels under impulse conditions.
test circuit
impulse, the high levels of electrical energy and rapid rates of change cause electrical noise to be induced or
conducted into the measurement system. It is possible for the electrical noise voltage to be many times the
wanted signal voltage. Elaborate wiring and measurement techniques where used to reduce the noise
voltage to less than 2 V peak to peak.
impulse generator
A Keytek ECAT E-Class series 100 with an E502 surge network was used for testing. The E502 produces a
0.5/700 voltage impulse. This particular waveform was used as it has the fastest rate of current rise (di/dt) of
the commonly used lightning surge waveforms. This maximises the measured limiting voltage. Figure 4
shows the current wavefront through the DUT. To produce a peak test current level of ±20 A, the E502
charging voltage was set to ±1960 V. Figure 5 shows the DUT current di/dt. Initially the wavefront current rises
at 60 A/µs, this rate then reduces as the peak current is approached. At the TISPPBL2S V
(BO)
condition the
di/dt is about 50 A/µs.
limiting voltage levels
Fifty devices were measured in the test circuit of Figure 3. The 50 devices were made up from groups of 5
devices taken from 10 separately processed device lots. Figure 7 shows the total waveform variation of the
thyristor limiting voltage across the 50 devices. This shows that the largest peak limiting voltage (Breakover
voltage, V
(BO)
) is -62 V, a 12 V overshoot beyond the -50 V gate reference supply, V
GG
. The limiting voltage
exceeds the gate reference supply voltage level for a period (t
(BR)
) of about 0.4 µs.
PRODUCT
INFORMATION
9
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