RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Parameter1
Symbol Test Conditions
I/O Type
Units
LVTTL I/O
HSTL I/O
Min
2.5
Max Min Max
Data Setup4
Data Hold4
Notes:
tDS
trise = see above table
tfall = see above table
1.15
0.75
ns
ns
6
tDH
1.0
1. In LVTTL mode, timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for
3.3V I/O, and from 0.48 x VccIO of clock to 0.48 x VccIO of signal for 2.5V I/O. In HSTL mode,
timings are measured from the crossing point of SysClock and SysClock* to 0.75V of the crossing
point of the signal.
2. Capacitive load for all LVTTL maximum output timings is 50 pF. Minimum output timings are for
capacitive load of 20 pF.
3. Capacitive load for all HSTL minimum and maximum output timings is 20 pF.
4. Data Output timing applies to all signal pins whether tristate I/O or output only.
5. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
6. Only mode[108:107:62:15:14]=11110 is tested in HSTL Class I mode during production test.
7. Data shown is for 3.3 V I/O. For 2.5 V I/O derate tDO Max by 0.5 nS, and tDO Min by 0.25 ns.
14.4 Boot-Time Interface Parameters
Parameter
Symbol
tDS
Min
4
Max
Units
Mode Data Setup
Mode Data Hold
SysClock cycles
SysClock cycles
tDH
0
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
65
PMC [ PMC-SIERRA, INC ]
