RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
4.4.2.15 PLL Control/Status
Symbol:
XPLL
Address Offset: 00100h
Default Value: 0001447Ch
Access:
Read/Write
Controls operation of the internal PLL (Phase locked loop). After a power on reset the PLL itself is held in
reset. This is reflected in bit 16 of this register. The local CPU must reset this bit to 0 to enable operation of
the device, and thus should write 0000447Ch to this register.
Bit
Description
31:17 PLL status. These bits reflect internal PLL operation status and should be ignored.
Reset PLL. When set to 1 the PLL is held reset. The supplied reference clock will be used as
16
the internal clock. The serial links will not be operational. This bit will be 1 after power-up reset
and should be deasserted for normal operation. PLL reset takes 10mS to complete.
15:0
PLL control.
236
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
