PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Data
Bits
Description
31:7
6:0
Reserved.
Requests
3.4.2.61 Waiting Scheduler Request Count Memory
Symbol: EWSRCT
Address Offset: 1C000-1DFFCh
Default Value: Unknown
Access:
Read/Write
The Waiting Scheduler request Count Memory contains the number of requests that the EPP is waiting to
get a grant back from the Scheduler. This memory is addressed by QID, but only Unicast and Multicast
addresses are valid. After resetting an EPP, write 00000000h to address offsets 1D000h through 1D7FCh
in that EPP (a total of 512 OOB writes). Whan all EPPs are reset simultaneously (using a broadcast OOB
write to the EPP Reset and Control register), 512 broadcast OOB writes can be used to reset those
locations in all EPPs.
For Unicast traffic: 128-512 queues depending on Egress OC-48c Mode Map register; maximum 64
requests for OC-192c, max 16 requests for OC-48.
Address
Bits
Description
19:13 Must be set to 0xE
12:11 Must be set to 0x2 for Unicast traffic type
10:9
8:4
3:2
1:0
Priority
Destination Port
Destination Subport
Must be set to 0
Data
Bits
Description
31:7
6:0
Reserved.
Requests
204
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
