Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 50. Illustrating the Flow of Cells from the Linecard CPU to the ETT1 CPU
Portcard
Linecard
Dataslice (6 of)
Fiber Link
CPU
OOB
EPP
Satellite
OOB
Controller
ETT1 CPU
The shallow queues on the left are simply rate-matching FIFOs of 8 cells depth, used to compensate for
asynchrony between the ETT1 core 200MHz clock and the 150MHz Serdes clock. The deeper queues on
the right represent the virtual output queues and virtual input queues, where cells are stored pending being
forwarded to their egress port or on to the linecard. We assume the presence of a linecard CPU which can
generate and receive Control cells to/from the ETT1 portcard
1.12.3.1 Verifying the Fiber Link
In order to verify that the optical fiber link between linecard and portcard is operational, the portcard can
set its local Serdes devices to operate in remote loopback mode. In addition the Dataslice devices can
operate in a remote loopback mode in which cells received at the ingress are looped back directly to the
egress rate matching FIFOs. Using either point of loopback the linecard can send cells to the portcard and
have them looped back directly so that the linecard can check the cells itself. This can provide a useful
post-failure diagnostic to determine if a fault is in the link or within the portcard or linecard. Figure 51 shows
the loopback path.
110
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
