RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Appendix B. Common Pinout
Configuration
B.1 JTAG INTERFACE
The ETT1 Chip Set supports the following JTAG public instructions in conformance with the IEEE Std
1149.1 specification:
•
•
•
•
IDCODE = b100
BYPASS = b111
EXTEST = b000
SAMPLE/PRELOAD = b010
As part of that standard, the following pins are used on each of the ETT1 Chip Set devices.
jtag_tck, jtag_tdi, jtag_tdo, jtag_tms, jtag_trst_L
The id codes used for the ETT1 Chip Set are as follows:
Dataslice
14367049h
Enhanced Port Processor 14581049h
Crossbar
14372049h
14374049h
Scheduler
B.2 RESERVED MANUFACTURING TEST PINS
Each device in the ETT1 Chip Set has a number of manufacturing test pins. These pins are reserved for
use during the manufacturing process. For functional operation, input test pins must be driven by a voltage
source, while output test pins should be left unconnected. Depending on conventions used during PCB
assembly, test inputs can be tied with a 1k ohm resistor to the appropriate VDD or GND supply. Such a
convention allows for onboard test operation for unusual diagnostic purposes. Test outputs should still be
soldered to the PCB for proper thermal and mechanical operation, and these outputs are often brought to
the solder (bottom) side of the board through vias for standard test fixtures.
For correct functional operation of the ETT1 devices, the following test inputs should be tied to VDD
through a resistor:
lssd_ce1_a, lssd_ce1_b, lssd_ce1_c1, lssd_ce1_c2, lssd_ce1_c3,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
323
PMC [ PMC-SIERRA, INC ]
