RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
test_ri, test_lt,
lssd_scan_in[0:15],
plltest_in
The following test inputs should be tied to GND through a resistor:
ce0_io, ce0_scan, ce0_test, ce0_tstm3,
test_re
The following test outputs should be left floating:
lssd_scan_out[0:15],
mon[0:15],
plltest_out
The following test inputs must be driven low during reset and high during operation. These can be
connected to the same reset signal used for the pwrup_reset_in_L input.
NOTE: These inputs can also driven low during board assembly tests to tristate all outputs.
Testing of board continuity can done during ICT.
test_di1, test_di2
The following test output could be left floating. Optionally, it may be used to monitor that the internal PLL
has locked to the ref_clk/ref_clkn inputs by checking the signal level during ETT1 operation.
plllock
B.3 POWER SUPPLY CONNECTIONS
All supply inputs labeled VDD must be driven by a common 2.5 V (nominal) supply.
All supply inputs labeled GND must be tied to a common (0 V) ground.
All pins labeled UNUSED must not be tied to a power or ground plane.
The supply input labeled VDDA must be connected to the common 2.5 V supply through a noise isolation
circuit. One possible method is shown in Figure 86.
324
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
