RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 60. AC Electrical Characteristics for 3.3V-tolerant 2.5V CMOS (Serdes Interface)
Symbol
Parameter
InputSetup
Input Hold
Conditions
Min
453
970
Typ
Max
Units
tsu3
th3
Trf=500 ps
Referenced to
forx0_clk, forx1_clk
ps
a
tval3
OutputValid
2.45
2.87
R1=50 Ohm, C1=1 pF
Referenced to
tsus3
OutputSustain
Output
Rise/Fall Time
a
fotx_clk_out,
tr3, tf3
ns
0.7
tper3
tph3
tpl3
ClockPeriod
ClockPulseHigh
ClockPulseLow
6.67
3.33
Defines
fotx_clk_in,
forx0_clk, forx1_clk
a. This parameter is not tested. It is provided here as a reasonable guide to design, based on expected
process parameters.
Table 61. Reference Clock for 200 Mbps HSTL (EPP/DS Interface)
Symbol
tsu4
Parameter
InputSetup
Input Hold
Conditions
Min
530
500
Typ
Max
Units
Trf=700 ps
Referenced to
ref_clk, ref_clkn
th4
tval4
OutputValid
2200
ps
Class1: R1=R2=100
Ohm, C1=1 pF
Referenced to
tsus4
OutputSustain
800
Output
Rise/Fall Time
a
ref_clk, ref_clkn
tr4, tf4
520
a. This parameter is not tested. It is provided here as a reasonable guide to design, based on expected
process parameters.
NOTE: Does not include Static Phase Offset or Jitter ( See Table 64 on page 308)
306
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
