RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 64. Jitter and Static Phase Offset for PLL
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PLL Jitter - Cycle to
Cycle
a
tccj
tltj
100
PLL Long-term
Jitter or Device to
Device
a
ps
400
PLL Static Phase
Offset
a
tpos
200
a. This parameter is not tested. It is provided here as a reasonable guide to design, based on expected
process parameters.
6.6 TIMING DIAGRAMS
Figure 69. Setup and Hold for 3.3V-tolerant 2.5V CMOS and 2.5V CMOS (OOB Interface)
Reference Clock
tval1
tsus1
Output
tsu1
th1
Input
308
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
