Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.9.5 Refresh Schedulers After Modifying Registers
The CPU cannot guarantee to modify the same register in both Schedulers at exactly the same instant,
even using an OOB multicast write to all Schedulers. Consequently there are certain Scheduler registers
which, when modified, require a refresh process to occur (assuming a system with two Schedulers). Table
20 list these registers.
Table 20. Refresh-sensitive Registers in the Scheduler
Address
00004h
Access
Register
Symbol
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Control and Reset
Enable Port
SCTRLRS
SENBPRT
SNTDMEN
STDMEN
SPORTRS
SPORTFRZ
STDMCTRL
SPLL
00038H
00080h
00084h
00088h
0008Ch
0009Ch
00100h
Enable non-TDM Traffic
Enable TDM Traffic
Reset Port
Freeze Port
TDM Control
PLL control/status
1.9.6 Hard Errors
This section describes the sequence of events that need to take place to correctly replace a failed board.
When a board is replaced, it must be resynchronized with an already running system. In this section, we
address each type of board replacement and describe how to resynchronize the board.
1.9.6.1 Port Board
When a port board fails, the Schedulers must disable traffic flowing to/from this port. All the cells currently
stored in the input and output queues of the failed port board will be lost. These are the following steps
required to replace the failed port board.
NOTE: The failure of the port board may also cause the primary Scheduler to shut down.
1. Detect failed port board.
2. Disable TDM and best-effort traffic in the Scheduler(s) to/from this port.
3. Disable this port in the Scheduler’s SENBPRT register.
4. Disable the AIB links to/from the Crossbars and Schedulers.
5. Replace failed port board.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PMC [ PMC-SIERRA, INC ]
