NSE-8G™ Standard Product Data Sheet
Preliminary
Register 00CH: NSE-8G Subsystem Interrupt Enable Register
Bit
Type
R
Function
Unused
Default
Bit 31:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
TOPINTE
CSUINTE
R8TDINTE
T8TEINTE
ILCINTE
DCBINTE
This register allows the CPU to disable or enable NSE-8G Subsystem interrupts with a single
write.
TOPINTE
This bit, when ‘1’, enables the generation of interrupts from the Top_level i.e.
R8C1EXTRAINT and R8C1MISSINT interrupts. When set to ‘0’ R8C1EXTRAINT and
R8C1MISSINT interrupts are disabled .
CSUINTE
This bit, when ‘1’, enables the generation of interrupts from CSU1 control. When set to ‘0’
CSU1 control interrupts are disabled .
R8TDINTE
This bit, when ‘1’, enables the generation of interrupts from R8TD blocks. When set to ‘0’ all
R8TD interrupts are disabled .
T8TEINTE
This bit, when ‘1’, enables the generation of interrupts from T8TE blocks. When set to ‘0’ all
T8TE interrupts are disabled .
ILCINTE
This bit, when ‘1’, enables the generation of interrupts from ILC blocks. When set to ‘0’ all
ILC interrupts are disabled .
DCBINTE
This bit, when ‘1’, enables the generation of interrupts from the DCB block. When set to ‘0’
DCB interrupts are disabled .
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
71
PMC [ PMC-SIERRA, INC ]
