NSE-8G™ Standard Product Data Sheet
Preliminary
Register 009H: NSE-8G Master Clock Monitor
Bit
Bit 31:2
Bit 1
Bit 0
Type
Function
Unused
RC1FPA
SYSCLKA
Default
R
R
R
X
X
X
When a monitored clock signal makes a low to high transition, the corresponding register bit is
set high. The bit will remain high until this register is read, at which point all the bits in this
register are cleared. A lack of transitions is indicated by the corresponding register bit reading
low. This register should be read at periodic intervals to detect clock failures.
SYSCLKA
The SYSCLK active bit (SYSCLKA) detects low to high transitions on the SYSCLK input.
SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read.
RC1FPA
The RC1FP active bit (RC1FPA) detects low to high transitions on the RC1FP input.
RC1FPA is set high on a rising edge of RC1FP, and is set low when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
68
PMC [ PMC-SIERRA, INC ]
