NSE-8G™ Standard Product Data Sheet
Preliminary
Register 00BH: NSE-8G Interrupt Enable Register
Bit
Bit 31:1
Bit 0
Type
R
R/W
Function
Unused
INTE
Default
X
0
This register allows the CPU to disable or enable NSE-8G interrupts with a single write.
INTE
This bit, when ‘1’, enables the INTB pin on the NSE. When set to ‘0’ INTB is held ‘1’.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
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