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PM8621 参数 Datasheet PDF下载

PM8621图片预览
型号: PM8621
PDF下载: 下载PDF文件 查看货源
内容描述: NSE- 8G⑩标准产品数据表初步 [NSE-8G⑩ Standard Product Data Sheet Preliminary]
分类和应用:
文件页数/大小: 184 页 / 957 K
品牌: PMC [ PMC-SIERRA, INC ]
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NSE-8G™ Standard Product Data Sheet  
Preliminary  
Field Name  
Page[1:0]#  
NSE-8G to SBS  
SBS to NSE  
Each bit indicates which control page  
to use, page 1 or 0, two bits, bit 1 for  
the ingress MSU and bit 0 for the  
egress MSU.  
Each bit shows current control page in  
use, page 1 or 0, two bits, bit 1 for the  
ingress MSU and bit 0 for the egress  
MSU.  
Only transmitted from the beginning of Only transmitted from the beginning of  
the first message of the frame  
the first message of the frame.  
User[2:0]#  
Aux[7:0]#  
User defined register indication to  
SBS reflected in the SBS as external  
hardware signal outputs.  
User defined register indication to  
NSE-8G from external hardware  
inputs to the SBS.  
Transmitted immediately.  
Transmitted immediately.  
User defined auxiliary register  
User defined auxiliary register  
indication to SBS.  
indication to NSE.  
Transmitted immediately.  
Transmitted immediately.  
# Change in these bits(received side) will not be processed if the received message CRC-16  
indicates an error.  
Interrupts can be generated when CRC errors are detected or the USER or LINK bits change  
state. There is no inherent flow control provided by the In-Band Link Controller. The attached  
microprocessor is able to provide flow control via interrupts when the in-band message FIFO  
overflows and via the USER and Auxiliary bits in the header.  
As each message arrives, the CRC-16 and valid bit is checked; if the valid bit is not set the  
message is discarded, if it fails the CRC check it is flagged as being in error and an interrupt is  
generated if enabled. If the CRC-16 is OK, regardless of the valid bit, the Page Link, User and  
Aux bits are passed on immediately. If the FIFO erroneously overflows, an interrupt is generated.  
9.10 Microprocessor Interface  
The following register map, Table 6, shows the registers used to provide control of the NSE.  
The first 100h addresses provide access to the top level NSE-8G configuration and control  
registers, the Clock synthesis units through the CSTR blocks and the DSO Crossbar (DCB) The  
DCB is the space switch at the core of the NSE. From 100h are 12 identical, 20h spaces used to  
control the ports of the NSE-8G on an individual basis. Each port has an In-Band Link Controller  
(ILC), an 8B/10B encoder (T8TE) and an 8B/10B decoder (R8TD). These blocks provide  
functions specific to the ports such as Line Code Violation counts (for data integrity monitoring)  
and receive and transmit in-band link message buffers. Only port 0 is fully described as the other  
ports are identical, being incrementally distributed from address 100h in 20h steps.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-2010850, Issue 1  
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