NSE-8G™ Standard Product Data Sheet
Preliminary
Table 4 Switching Control RAM Layout
Control Page 0
Control Page 1
Col
RAM Address STS
Row
1
Col
1
STS
Row
0
1
1
1
1
1
2
1
1
2
1
1
…
9719
…
12
9
90
12
9
90
The multiplexers that select the inputs for each egress port are straight forward 12 to-1
multiplexers. They require five bits of control during each 77.76 MHz clock cycle. Their outputs
go to the T8TEs. This design permits unicast, multicast, and broadcast.
9.5
9.6
Clock Synthesis and Transmit Reference Digital Wrapper (CSTR)
The CSTR contains the configuration registers for the CSU and TXREF LVDS analog locks.
Fabric Latency
The flow of octets from ingress LVDS to egress LVDS has variable latency, depending on the
timing of the arriving LVDS stream, and the clock variation on the egress LVDS drivers. A
reasonable estimate of the NSE’s latency can be arrived at by making assumptions about the
depths of the receive and transmit FIFOs: we assume the “C1” timing is set to maintain about
four samples in the ingress FIFO; the egress FIFO is designed to be centered at four samples – so
typically delay due to FIFOs will be 8 clock cycles. The latency through the space switch stage is
three clock cycles. Data latency through the analog blocks is around 90 ns. The typical latency of
the NSE-8 G is 24 clock cycles or 308 ns. With worst case conditions in both FIFOs, latency rises
to 36 clock cycles or 463 ns.
9.7
9.8
JTAG Support
The NSE-8G provides JTAG support for testing device interconnection on a PC board.
Microprocessor Interface
The Microprocessor Interface Block provides the logic required to interface the normal mode and
test mode registers within the NSE-8G to a generic microprocessor bus. The normal mode
registers are used during normal operation to configure and monitor the NSE. The register set is
accessed as shown in the Register Memory Map table below. Addresses that are not shown are
not used and must be treated as Reserved.
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Document ID: PMC-2010850, Issue 1
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