NSE-8G™ Standard Product Data Sheet
Preliminary
Pad Name
NC[49:0]
Type
Pin No.
D17
B17
A17
D25
C25
D26
B26
A26
C27
B27
C28
B28
A28
480
Function
TOTAL
Notes
1. All NSE-8G inputs and bi-directional balls except the LVDS links present minimum capacitive loading
and operate at TTL logic levels.
2. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
3. All outputs have a minimum 8 mA drive capability – this includes TDO, INTB and D[31:0]).
4. The VDDI and AVDL power pins are not internally connected to each other. Failure to connect these
pins externally may cause malfunction or damage to the device.
5. The AVDH, CSU_AVDH and VDDO power pins are not internally connected to each other. Failure to
connect these pins externally may cause malfunction or damage to the device.
6. The VDDI, VDDO, AVDH, CSU_AVDH and AVDL power pins all share the common ground VSS.
7. To prevent damage to the device and to ensure proper operation, power must be applied
simultaneously to all 3.3 V power pins followed by power to all the 1.8 V power pins followed by input
pins driven by signals.
8. To prevent damage to the device, power must first be removed from input pins followed by the removal
of power from all the 1.8 V power supply pins followed by the simultaneous removal of power from all
the 3.3 V power pins.
9. The 3.3 V supplies should never be less than the 1.8 V supplies at any time during power-up and
power-down.
8.2
Analog Power Filtering Recommendations
To achieve best performance of the LVDS links, an analog filter network should be installed
between the power balls and the supply.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
38
PMC [ PMC-SIERRA, INC ]
