NSE-8G™ Standard Product Data Sheet
Preliminary
9
Functional Description
9.1
LVDS Overview
The LVDS family of cells allow the implementation of 777.6 Mbit/s LVDS links. A reference
clock of 77.76 MHz is required.
A generic LVDS link according to IEEE 1596.3-1996 is illustrated in Figure 7 below. The
transmitter drives a differential signal through a pair of 50 Ω characteristic interconnects, such as
board traces, backplane traces, or short lengths of cable. The receiver presents a 100 Ω
differential termination impedance to terminate the lines. Included in the standard is sufficient
common-mode range for the receiver to accommodate as much as 925 mV of common-mode
ground difference.
Figure 8 Generic LVDS Link Block Diagram
Transmitter
Interconnect
Receiver
Zo=50Ω
V
op
on
V
ip
in
100Ω
V
V
Zo=50Ω
Complete SERDES transceiver functionality is provided. Ten-bit parallel data is sampled by the
line rate divided-by-10 clock (77.76 MHz SYSCLK) and then serialized at the line rate on the
LVDS output pins by a 777.6 MHz clock synthesized from SYSCLK. Serial line rate LVDS data
is sampled and de-serialized to 10-bit parallel data. Parallel output transfers are synchronized to a
gated line rate divided-by-10 clock. The 10-bit data is passed to an 8B/10B decoding block. The
gating duty cycle is adjusted such that the throughput of the parallel interface equals the receive
input data rate (Line Rate +/- 100 ppm). It is expected that the clock source of the transmitter is
the same as the clock source of the receiver to ensure the data throughput at both ends of the link
are identical.
Data is guaranteed to contain sufficient transition density to allow reliable operation of the data
recovery units by 8B/10B block coding and decoding provided by the T8TE and R8TD blocks.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
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