NSE-8G™ Standard Product Data Sheet
Preliminary
Pad Name
VSS [71:0]
Type
Ground
Pin No.
K34
Function
M34
P34
W34
AA34
AC34
AE34
AG34
AJ34
AL34
AM34
AN34
Analog Power (8 Balls)
AVDL[7:0]
Power
F31
N33
W33
AD32
AJ4
AB2
T2
The analog power pins (AVDL[7:0]) should be connected
to a well-decoupled +1.8 V DC supply. These pins
supply the RXLVs.
L3
Clock Synthesis 1.8 V Power (6 Balls)
CSU_AVDL[5:0] Power
T31
T32
U32
W4
W3
V3
The clock synthesis pins (CSU_AVDL[5:0]) should be
connected to a well-decoupled +1.8 V DC supply. These
pins supply the CSUs.
Clock Synthesis Power (2 Balls)
CSU_AVDH[0:1] Power
U31
V4
These two pins should be connected to a well-decoupled
+3.3 V DC supply.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
35
PMC [ PMC-SIERRA, INC ]
