NSE-8G™ Standard Product Data Sheet
Preliminary
Pad Name
Type
Pin No.
Function
Microprocessor Interface (49 Balls)
CSB
Input
AM30
Chip Select Bar. The active low chip select signal (CSB)
controls microprocessor access to registers in the NSE-
8G device. CSB is set low during NSE-8G
Microprocessor Interface Port register accesses. CSB is
set high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled
using RDB and WRB signals only), CSB should be
connected to an inverted version of the RSTB input.
Read Enable Bar. The active low read enable bar signal
(RDB) controls microprocessor read accesses to
registers in the NSE-8G device. RDB is set low and CSB
is also set low during NSE-8G Microprocessor Interface
Port register read accesses. The NSE-8G drives the
D[31:0] bus with the contents of the addressed register
while RDB and CSB are low.
Write Enable Bar. The active low write enable bar signal
(WRB) controls microprocessor write accesses to
registers in the NSE-8G device. WRB is set low and CSB
is also set low during NSE-8G Microprocessor Interface
Port register write accesses. The contents of D[31:0] are
clocked into the addressed register on the rising edge of
WRB while CSB is low.
RDB
Input
Input
AM29
AN29
WRB
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
27
PMC [ PMC-SIERRA, INC ]
