NSE-8G™ Standard Product Data Sheet
Preliminary
Pad Name
TP[1]
TN[1]
TP[2]
TN[2]
TP[3]
TN[3]
TP[4]
Type
Pin No.
F2
F3
G1
G2
G3
G4
J1
Function
Transmit Serial Data. The differential transmit working
serial data links (TP[11:0]/TN[11:0]) carry the transmit
SBI336S or SONET/SDH STS-12 frame data to a
downstream sinks in bit serial format. Each differential
pair carries a constituent STS-12 stream. Data on
TP[X]/TN[X] is encoded in an 8B/10B format extended
from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is
transmitted first and the bit ‘j’ is transmitted last. All
TP[X]/TN[X] differential pairs are frequency locked and
phase aligned (within a certain tolerance) to each other.
TP[11:0]/TN[11:0] are nominally 777.6 Mbit/s data
streams.
Analog
LVDS
Output
TN[4]
TP[5]
J2
N1
TN[5]
TP[6]
N2
N3
TN[6]
TP[7]
N4
P2
TN[7]
TP[8]
P3
R1
TN[8]
TP[9]
R2
W1
W2
Y3
Y4
Y1
Y2
AA2
AA3
TN[9]
TP[10]
TN[10]
TP[11]
TN[11]
TP[12]
TN[12]
NSE-8G Control and Clocking (5 Balls)
SYSCLK Input
A16
System Clock. The system clock signal (SYSCLK) is the
master clock for the NSE-8G device. SYSCLK must be a
77.76 MHz clock, with a nominal 50% duty cycle.
CMP and RC1FP are sampled on the rising edge of
SYSCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
25
PMC [ PMC-SIERRA, INC ]
