NSE-8G™ Standard Product Data Sheet
Preliminary
12 Operation
There are several important aspects regarding the operation of NSE-based switch fabrics; these
are dealt with in turn in the following sections.
12.1 Software Default Settings
12.1.1 Setting the T8TE Time-slot Configuration #1 Register
Set the first T8TE Time-slot Configuration register to 0000AAAAh. This sets T8TE to LPT mode
so that Low Order Path signals are encoded in outgoing 8B/10B characters. Or, set to 00005555h
to set T8TE to HPT mode to ensure V1/V2 bytes are preserved.
12.1.2 Setting the T8TE Time-slot Configuration #2 Register
Set the second T8TE Time-slot Configuration register to 000000Aah. This sets T8TE to LPT
mode so that Low Order Path signals are encoded in outgoing 8B/10B characters. Or, set to
00000055h to set T8TE to HPT mode to ensure V1/V2 bytes are preserved.
12.1.3 Configuring the NSE-8G to Use Fewer Links
The NSE-8G powers up with the software digital reset disabled, software analog reset disabled
and individual link reset enabled. This means that only the digital blocks are enabled post
hardware reset (since setting channel reset also disable the associated analog blocks). The CSU
by default will be start upon NSE-8G powers up; it can only be reset by the firmware writing
logic one to the ARESET bit in NSE-8G Master Reset register (000H). By writing logic zero to
appropriate channels in NSE-8G Individual Channel Reset register (001H) will bring the
associated link out of reset and operational for normal mode operation.
When fewer than 32/12 links are used in the NSE-8G 20G/8G, the unused links should be
disabled individually by writing logic one to the appropriate NSE-8G Individual Channel Reset
register (001H) bit. Writing logic one to bit N of NSE-8G Individual Channel Reset register will
disable the R8TD, ILC, and T8TE of channel N. This reset controls both the digital as well as the
analog reset inputs of the R8TD and T8TE. The analog reset input of R8TD and T8TE gates the
analog reset and enable output that is used to disable the associated DRU/RXLV, PISO/TXLV
analog blocks. This will cause the entire link from input N to output N to be disabled.
Reset States of Various Operation Modes
Post Hardware Reset:
Register 000H : DRESET
Register 000H : ARESET
Register 001H : RESET
‘0’
‘0’
‘0xFFFFFFFF’
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
134
PMC [ PMC-SIERRA, INC ]
