PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Figure 2 – CRC Generator
g
g
g
n-1
1
2
Message
D
D
D
D
n-1
0
1
2
LSB
Parity Check Digits
MSB
8.3 SBI Extracter and PISO
The SBI receive circuitry consists of an SBI Extract block and three SBI Parallel
to Serial Converter (SBI PISO) blocks. The SBI Extract block receives data from
the SBI DROP BUS and converts it to an internal parallel bus format. The
received data is then converted to serial bit streams by the PISO blocks. Each
PISO block processes one of the three Synchronous Payload Envelopes (SPEs)
conveyed on the SBI DROP BUS.
The SBI Extract block may be configured to enable or disable reception of
individual tributaries within the SBI DROP bus. Individual tributaries may also be
configured to operate in framed or unframed mode.
Each PISO block processes data from one SPE on the internal parallel bus and
generates either 28 serial data streams at T1/J1 rate, 21 streams at E1 rate or a
single stream at DS-3 rate. These serial streams are then processed by the
Receive Channel Assigner block.
8.4 Receive Channel Assigner
The Receive Channel Assigner block (RCAS672) processes up to 84 serial links.
When receiving data from the SBI PISO blocks, links may be configured to
support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed
traffic at T1/J1, E1 or DS-3 rates. When receiving data from the RCLK/RD
inputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 51.84
Mbps.
Each link is independent and has its own associated clock. For each link, the
RCAS672 performs a serial to parallel conversion to form data bytes. The data
bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC
Processor / Partial Packet Buffer block (RHDL672) at SYSCLK rate. In the event
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
