PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x40C : TCAS Idle Time-slot Fill Data
Bit
Type
Function
Default
Bit 15
to
Unused
XXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FDATA[7]
FDATA[6]
FDATA[5]
FDATA[4]
FDATA[3]
FDATA[2]
FDATA[1]
FDATA[0]
1
1
1
1
1
1
1
1
This register contains the data to be written to disabled time-slots of a
channelised link.
FDATA[7:0]:
The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low)
time-slots of channelised links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
144
PMC [ PMC-SIERRA, INC ]
