PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
RMAC672 block without having to precisely track the number of full blocks in the
channel FIFO.
The partial packet roamer performs the transaction accounting for all channel
FIFOs. The roamer increments the transaction count when the writer signals a
new transaction and sets a per-channel flag to indicate a non-zero transaction
count. The roamer searches the flags in a round-robin fashion to decide for
which channel FIFO to request transfer by the RMAC672 block. The roamer
informs the partial packet reader of the channel to process. The reader transfers
the data to the RMAC672 until the channel transfer size is reached or an end of
packet is detected. The reader then informs the roamer that a transaction is
consumed. The roamer updates its transaction count and clears the non-zero
transaction count flag if required. The roamer then services the next channel
with its transaction flag set high.
The writer and reader determine empty and full FIFO conditions using flags.
Each block in the partial packet buffer has an associated flag. The writer sets
the flag after the block is written and the reader clears the flag after the block is
read. The flags are initialized (cleared) when the block pointers are written using
indirect block writes. The writer declares a channel FIFO overrun whenever the
writer tries to store data to a block with a set flag. In order to support optional
removal of the FCS from the packet data, the writer does not declare a block as
filled (set the block flag nor increment the transaction count) until the first double
word of the next block in channel FIFO is filled. If the end of a packet resides in
the first double word, the writer declares both blocks as full at the same time.
When the reader finishes processing a transaction, it examines the first double
word of the next block for the end-of-packet flag. If the first double word of the
next block contains only FCS bytes, the reader would, optionally, process next
transaction (end-of-packet) and consume the block, as it contains information not
transferred to the RMAC672 block.
9.6 Receive DMA Controller
The Receive DMA Controller block (RMAC672) is a DMA controller which stores
received packet data in host computer memory. The RMAC672 is not directly
connected to the host memory PCI bus. Memory accesses are serviced by a
downstream PCI controller block (GPIC). The RMAC672 and the host exchange
information using receive packet descriptors (RPDs). The descriptor contains
the size and location of buffers in host memory and the packet status information
associated with the data in each buffer. RPDs are transferred from the
RMAC672 to the host and vice versa using descriptor reference queues. The
RMAC672 maintains all the pointers for the operation of the queues. The
RMAC672 provides two receive packet descriptor reference (RPDR) free queues
to support small and large buffers. The RMAC672 acquires free buffers by
reading RPDRs from the free queues. After a packet is received, the RMAC672
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
