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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
SBI  
SBI  
RCAS  
SBI  
SBI  
RCAS  
Link  
No.  
SBI  
SBI  
RCAS  
Link  
No.  
SPE Trib.  
Link  
No.  
SPE Trib.  
SPE Trib.  
No.  
1
No.  
23  
No.  
2
No.  
23  
No.  
3
No.  
23  
66  
69  
72  
75  
78  
81  
67  
70  
73  
76  
79  
82  
68  
71  
74  
77  
80  
83  
1
1
1
1
1
24  
25  
26  
27  
28  
2
2
2
2
2
24  
25  
26  
27  
28  
3
3
3
3
3
24  
25  
26  
27  
28  
Links containing a T1/J1 or an E1 stream may be channelised. Data at each  
time-slot may be independently assigned to a different channel. The RCAS672  
performs a table lookup to associate the link and time-slot identity with a  
channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame  
pulse signals generated by the SBI PISO blocks. Links containing a DS-3  
stream are unchannelised, i.e. all data on the link belongs to one channel. The  
RCAS672 performs a table lookup using only the link number to determine the  
associated channel, as time-slots are non-existent in unchannelised links. Links  
may additionally be configured to operate in an unframed “clear channel” mode,  
in which all bit positions, including those normally reserved for framing  
information, are assumed to be carrying HDLC data. Links so configured  
operate as unchannelised regardless of link rate and the RCAS672 performs a  
table lookup using only the link number to determine the associated channel.  
9.4.1 Line Interface  
There are 84 line interface blocks in the RCAS672. Each line interface block  
contains a bit counter, an 8-bit shift register and a holding register that, together,  
perform serial to parallel conversion. Whenever the holding register is updated,  
a request for service is sent to the priority encoder block. When acknowledged  
by the priority encoder, the line interface responds with the data residing in the  
holding register.  
To support channelised links, each line interface block contains a time-slot  
counter. The time-slot counter is incremented each time the holding register is  
updated and is reset on detection of a frame pulse from the SBI PISO blocks.  
For unchannelised or unframed links, the time-slot counter is held reset.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
37  
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