PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
The partial packet buffer processor is divided into three sections: writer, reader
and roamer. The writer is a time-sliced state machine which writes the HDLC
data and status information from the HDLC processor into a channel FIFO in the
packet buffer RAM. The reader transfers channel FIFO data from the packet
buffer RAM to the downstream Receive DMA Controller block (RMAC672). The
roamer is a time-sliced state machine which tracks channel FIFO buffer depths
and signals the reader to service a particular channel. If a buffer over-run
occurs, the writer ends the current packet from the HDLC processor in the
channel FIFO with an over-run flag and ignores the rest of the packet.
Figure 3 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
16 bytes
16 bytes
16 bytes
16 bytes
XX
0x03
XX
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
0xC8
16 bytes
16 bytes
0x01
XX
Block 200
Block 200
Block 2047
Block 2047
The FIFO algorithm of the partial packet buffer processor is based on a
programmable per-channel transfer size. Instead of tracking the number of full
blocks in a channel FIFO, the processor tracks the number of transactions.
Whenever the partial packet writer fills a transfer-sized number of blocks or
writes an end-of-packet flag to the channel FIFO, a transaction is created.
Whenever the partial packet reader transmits a transfer-size number of blocks or
an end-of-packet flag to the RMAC672 block, a transaction is deleted. Thus,
small packets less than the transfer size will be naturally transferred to the
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40
PMC [ PMC-SIERRA, INC ]
