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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
The initiator negates FRAMEB since this the last data phase of this cycle. The  
target claims the transaction by driving DEVSELB active and drives TRDYB to  
indicate to the initiator that it is ready to accept the data.  
During clock 3, the target latches in the data element and negates TRDYB and  
DEVSELB, having seen FRAMEB negated previously. The initiator negates  
IRDYB and drives FRAMEB to start the next cycle. It also drives the address  
onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command.  
In this example the command would indicate a burst write.  
During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus  
and starts driving the first data element. The initiator also drives the C/BEB[3:0]  
lines with the byte enables for the write data. IRDYB is driven active by the  
initiator to indicate that the data is valid. The target claims the transaction by  
driving DEVSELB active and drives TRDYB to indicate to the initiator that it is  
ready to accept the data.  
During clock 5, the initiator is ready to transfer the next data element so it drives  
the AD[31:0] lines with the second data element. The initiator negates FRAMEB  
since this is the last data phase of this cycle. The target accepts the first data  
element and negates TRDYB to indicate its is not ready for the next data  
element.  
During clock 6, the target is still not ready so a wait state shall be added.  
During clock 7, the target asserts TRDYB to indicate that it is ready to complete  
the transfer.  
During clock 8, the target latches in the last element and negates TRDYB and  
DEVSELB, having seen FRAMEB negated previously. The initiator negates  
IRDYB. All of the above signals shall be driven to their inactive state in this clock  
cycle, except for FRAMEB which shall be tristated. The target stops driving the  
AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall be the  
turnaround cycle for these signals.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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