PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
During clock 9, the initiator does not want to continue the lock so it negates
LOCKB. The target samples LOCKB and FRAMEB deasserted it removes its
lock.
Figure 33 – PCI Exclusive Lock Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
T
T
T
FRAMEB
AD[31:0]
Address
T
Data
Address Data
LOCKB
IRDYB
T
T
T
T
T
T
TRDYB
DEVSELB
Fast back-to-back transactions are used by an initiator to conduct two
consecutive transactions on the PCI bus without the required idle cycle between
them. This can only occur if there is a guarantee that there will be no contention
between the initiator or targets involved in the two transactions. In the first case,
an initiator may perform fast back-to-back transactions if the first transaction is a
write and the second transaction is to the same target. All targets must be able
to decode the above transaction. In the second case, all of the targets on the
PCI bus support fast back-to-back transactions, as indicated in the PCI Status
configuration register. The FREEDM-84P672 only supports the first type of fast
back-to-back transactions and is shown in Figure 34.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also
drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with
the write command. In this example the command would indicate a single write.
The IRDYB, TRDYB and DEVSELB signals are in turnaround mode and are not
being driven for this clock cycle. This cycle on the PCI bus is called the address
phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus
and starts driving the data element. The initiator also drives the C/BEB[3:0] lines
with the byte enables for the write data. IRDYB is driven active by the initiator to
indicate that the data is valid.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
330
PMC [ PMC-SIERRA, INC ]
